Editing ECE1373

The internet is big <ref>[http://bgp.potaroo.net/ BGP Reports: Growth of the BGP Table - 1994 to Present]</ref><ref>[http://www.icir.org/floyd/papers/simulate_2001.pdf Difficulties in Simulating the Internet]</ref>. Even individual applications (e.g. P2P) often involve interactions with a large number of nodes. Simulating large networks is slow in software, while simulations using clusters of CPUs is expensive. Current systems can emulate a few hundred nodes in ~real time <ref>[http://www.eecg.utoronto.ca/~bli/papers/crystal-icdcs08.pdf Crystal: An Emulation Framework for Practical Peer-to-Peer Multimedia Streaming Systems]</ref> (10-15k packets/s), while simulations can be somewhat faster (~1k nodes, >100k packets/s).

Given the independence of each network node and the tolerance of some amount of timing error, large-scale network simulations could be a good fit for parallel hardware acceleration. GPU acceleration may not be the ideal method, as there would be a large amount of communication between nodes ("threads"), and nodes would not often process in lock-step (SIMD/SIMT), but rather only in response to a packet.

== Network Simulator/Emulator on Chip ==

A collection of traffic generators and network links, with some nodes being routers. The objective being to model and observe behavior of large networks, faster and/or cheaper than software simulations.

== Goals ==
* Simulate hundreds of nodes at real-time or faster on one chip. 10-100M packets per second?

== Prior Art ==

* [[Related Work]]

== Architecture ==
=== Requirements ===
* Requires configurable network topology, latency/throughput, and some way of observing performance metrics.
* Debug features: clock freeze, register probing, clock-stepping etc.

=== Traffic Generation ===

Simple traffic generators in hardware that generate packets according to some distribution. One possibility being to generate a packet of configurable size periodically. Configuration (and statistics?) done using soft-processor, since configuration isn't time-sensitive.

Future work could include replacing simple traffic generators with (multithreaded) soft-processors to easily implement complex network protocols.

=== Routers ===
Not sure what to do about the routing table.

=== Network Links ===
Delay and bandwidth can be modeled by having a timestamp associated with each packet. Not sure how this might be implemented in hardware: Multiple queues per node seems difficult to manage. Perhaps by having dedicated "link" nodes on the chip, one per edge in the network graph, which essentially functions as the destination node's input queue.

'''argh'''. This is hard. Need to implement delay queues that do repeated subtraction instead of division, yet can generate an accurate timestamp several cycles in advance.

=== On-Chip Network ===
[[On-Chip Network]]

== Current Problems ==
* [[On-Chip Network]] design
* PacketQueue timestamp algorithm that does not require division (or multiplication), yet can provide a correct timestamp some cycles ahead of the timestamp's time. Alternatively, an interconnect design that does not require correct timestamp values (not likely).
* Relative timestamp instead of absolute ones
* Simulation time step should not advance when the a packet is forwarded to a queue from a router

=== Other Considerations ===
* Can't use discrete event simulation b/c maintaining a central event queue is not favourable for FPGA implementation. A distributed approach is better.

== Things that break ==
* [[ECE1373_Notes|Notes]]

== Verification ==
A performance [[Simulator]] that attempts to model cycle-accurate performance of the hardware design.

HDL [[Testbench]]es.

== HDL ==
Specification for various [[ECE1373_HDL|Hardware Modules]].

== Schedule ==

<!--{| border=1 style="border-collapse: collapse; border-width: 1px; border-style:solid; border-color: #abccde; margin:1.5em;" cellpadding=3
! style="width:200px" | Task !! Difficulty !! style="width:70px" | Date
|-
| Simulator || 1 || ~almost
|-
| Topology generator || 3 || [[Simulator#Topology_Generator|done]]
|-
| Interconnect || 2 || WW10
|-
| Queue timestamp scheme || 3 || WW11
|-
| Routing table scheme || 2 || WW12
|-
| Try SystemC, maybe || 4 || ?
|-
| HDL! || 5 || WW15
|- 
| Co-simulation || 3 || WW16
|- 
| Interface tools || 2 || WW18<br>(Apr 30!)
|}-->

[[Image:gantt_chart.png]]

== Stuff ==
svn://stuffedcow.net/ece1373/

Weekly [[ECE1373_Status|Status]]

[[:Image:Course_final.pdf|Final presentation slides]] <br>
[[:Image:Ece1373_Report.pdf|Final report]]

== References ==
<references />