Testbench
From Bits
[edit] top_tb
Top-level half-module, half-testbench. Instantiates and connects the other modules as a top-level entity, but written like a testbench so not synthesizable. Probably more maintenance work needed if we nicely separate the top-level into a synthesizable top-level module and a non-synthesizable testbench, so will have to do that later.
Currently contains the following (June 2):
- 1x PartitionPQ (ppq0)
- 1x TrafficGenDiv (tg0)
- 1x Bus1SourcePart (b1sp0)
- 1x Bus1DestPart (b1dp0)
- 1x PartitionRT (prt0)
- 1x pair of Router (rt0)
- 1x Bus0SourcePart (b0sp0)
- 1x Bus0DestPart (b0dp0)
Packets get generated, routed, and go back to the TG.
[edit] Funny stuff
- vsim -novopt
- Don't optimize away the design in modelsim...
